Random Access Memory (RAM) typically includes an array of memory cells arranged in rows (wordlines) and columns (bitlines). Each cell stores a single bit of data, namely a logic 0 or a logic 1. The intersection of a bitline and a wordline defines the address of a particular memory cell.
To read data in a memory cell, a memory system typically sends the address of that data to a memory controller that decodes the address of the data. The memory controller then uses the decoded address information to access data in the addressed memory cell by activating the particular wordline and bitline that the decoded address information specifies. Because semiconductor manufacturing processes are not 100% defect free, it is possible that an addressed wordline may exhibit a defect and thus yield defective data when the memory controller activates the defective wordline. To lessen the impact of such defects, memory systems may employ wordline/bitline redundancy control techniques. In conventional memory redundancy methodologies, when a decoded address points to a wordline containing a defect, the memory controller employs a mechanism that selects an alternative wordline to effectively bypass the defect.
Memory controllers may employ two stage address decoders that include an initial decode stage and a final decode stage. The initial decode stage pre-decodes a supplied memory address to determine which memory location the memory controller will access. The final decode stage uses the decoded address to activate a selected wordline and bitline to access the addressed memory location. The final decode stage accesses this memory location to either write data to, or read data from, the memory location. Conventional high performance memory systems may employ a decoder wherein the final decode stage shifts from a defective original wordline to an alternative substitute wordline when the memory system determines that the original wordline exhibits a defect. Another term for a substitute wordline is a redundant wordline, namely an extra wordline that is available should the memory system detect a defective wordline. If two adjacent wordlines exhibit defects or errors in a one-bit shift scheme, the final decode stage may shift one defective wordline up in the memory array and the other defective wordline down in the array to activate other available redundant wordlines. Decoders may employ shift registers to shift defective wordlines to redundant wordlines. By shifting wordlines in this manner, a memory controller can avoid or bypass memory defects. Memory controllers may employ the same approach to bypass defective bit lines.
While conventional memory systems can avoid defective wordlines by using redundant wordline methodology, unfortunately the resultant improvement in memory reliability comes at the price of a substantial increase in the amount of logic that the memory system employs. What is needed is a method and apparatus that provides redundancy in a memory system while reducing the complexity and size of the logic circuitry associated with the memory system.